2.4倍速実時間6万語彙連続音声認識プロセッサの開発 (集積回路)  [in Japanese] A 2.4x-Real-Time VLSI Processor for 60-k Word Continuous Speech Recognition  [in Japanese]

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Author(s)

Abstract

本稿では,6万語彙の実時間連続音声認識のための低消費電力VLSIチップについて説明する.GMM演算時の外部メモリ帯域削減用圧縮デコーダ,VITERBI並列アーキテクチャを実装した.内部SRAM容量を最適化するために,近似GMM演算アルゴリズムの導入,先読みフレーム数の調整を行った.その結果,実時間処理時において従来研究より必要動作周波数を34.2%削減し83.3MHz,消費電力を48.5%削減し74.14mWを実現した.また,標準電圧(1.1 V)で最大200MHz (168 mW) 動作を確認し,2.4倍速で動作することを確認出来た.

This paper describes a low-power VLSI chip for 60-kWord continuous speech recognition based on a context-dependent Hidden Markov Model (HMM). Our implementation includes a compression–decoding scheme to reduce the external memory bandwidth for Gaussian Mixture Model (GMM) computation and multi-path Viterbi transition units. We optimize the internal SRAM size using the max-approximation GMM calculation and adjusting the number of look-ahead frames. The measured results show that our implementation achieves 34.2% required frequency reduction (83.3 MHz) and reduces 48.5% power consumption (74.14 mW) for 60 k-Word real-time continuous speech recognition compared to the previous work. This chip can maximally process 2.4× faster than real-time at 200 MHz and 1.1 V with power consumption of 168 mW.

Journal

  • Technical report of IEICE. ICD

    Technical report of IEICE. ICD 112(365), 49-53, 2012-12-17

    The Institute of Electronics, Information and Communication Engineers

Codes

  • NII Article ID (NAID)
    110009667345
  • NII NACSIS-CAT ID (NCID)
    AN10013276
  • Text Lang
    JPN
  • ISSN
    0913-5685
  • NDL Article ID
    024196480
  • NDL Call No.
    Z16-940
  • Data Source
    NDL  NII-ELS 
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