招待講演 超低消費電力断熱モード磁束量子パラメトロンを用いた論理回路のシミュレーションと動作実証 (超電導エレクトロニクス)  [in Japanese] Simulation and Experimental Demonstration of Logic Circuits Using an Ultra-low-power Adiabatic Quantum-Flux-Parametron  [in Japanese]

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Author(s)

Abstract

我々はポテンシャル変化をゆっくり,あるいは断熱的に行うことでエネルキー消費を劇的に低減することか出来る超低消費断熱モード磁束量子パラメトロン(Adiabatic Quantum-Flux-Parametron:AQFP)論理の研究を行っている.本研究において我々は基本的なAQFPゲートと全加算器を設計し,それらの動作をシミュレーションと測定の両方て確認した.AQFP1ビット全加算器は46個のJosephson接合数で構成されており,この値は従来の単一磁束量子(Rapid Single-Flux-Quantum:RSFQ)回路による全加算器の4分の1程度の接合数となっている.また,全加算器の側定においてシミュレーションと同程度の±27.8%という広いマージンが得られた.

We have been investigating an ultra-low-power adiabatic quantum-flux-parametron (AQFP) logic, the energy dissipation of which can be decreased by changing its potential energy slowly or adiabatically In the present study, we designed basic AQFP gates and an AQFP 1-bit full adder, and examined their operations through simulations and experiments The AQFP 1-bit full adder is composed of 46 Josephson Junctions, which is approximately one-quarter the number of a full adder using conventional rapid single-flux-quantum logic The measurement results indicated that the AQFP 1-bit full adder has a wide current bias margin of as large as ±27.8%

Journal

  • Technical report of IEICE. SCE

    Technical report of IEICE. SCE 112(408), 37-42, 2013-01-24

    The Institute of Electronics, Information and Communication Engineers

Codes

  • NII Article ID (NAID)
    110009727943
  • NII NACSIS-CAT ID (NCID)
    AN10012885
  • Text Lang
    JPN
  • ISSN
    0913-5685
  • NDL Article ID
    024262672
  • NDL Call No.
    Z16-940
  • Data Source
    NDL  NII-ELS 
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