AVX2を用いた倍精度BCRS形式疎行列と倍々精度ベクトル積の高速化 AVX2 Acceleration of Double Precision Sparse Matrix in BCRS Format and DD Vector Product

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高精度演算を用いることでKrylov部分空間法の収束を改善できるが,高精度演算はコストが高いことが知られている.高精度演算の1つに,倍精度を2つ組み合わせて4倍精度演算を行う倍々精度演算がある.我々は,IntelのSIMD拡張命令であるAVX2を用いてBCRS形式の倍精度疎行列と倍々精度ベクトルの積(DD-SpMV)の高速化を行った.AVX2を用いたCRS形式のDD-SpMVでは,各行で端数処理などを必要とするが,BCRS形式は端数処理をなくし,メモリアクセスを改善できる.しかし,BCRS形式は演算量が増加する.本論文では,AVX2に適したBCRS形式のブロックサイズと,増加した演算量と端数処理の削減,メモリアクセスの改善効果のトレードオフについて示した.実験の結果,AVX2に最も適したブロックサイズは4×1であることが分かった.また,メモリアクセスの改善効果はサイズの大きい問題ほど有効で,行列サイズが10 5以上のとき,演算量が3.3倍以上になるケースにおいても,BCRS4×1にすることでCRS形式の実行時間を約45%に短縮できることを確認した.High precision arithmetic can improve the convergence of Krylov subspace methods; however, it is very costly. One system of high precision arithmetic is Double-Double arithmetic, which uses two double precision variables to implement one quadruple precision variable. We accelerated double sparse matrix in BCRS format and DD vector product (DD-SpMV) using AVX2. DD-SpMV in CRS format using AVX2 needs fraction processing each row. BCRS format which aligns the SIMD register's length can eliminate fraction processing and improve memory access. However, it may increase operations. In this paper, we have shown that trade-off between increased operations and eliminated fraction processing and improving memory access. In experimental results, we concluded that the best BCRS block size is BCRS4×1. The effect of improving memory access in BCRS format depends on matrix sizes. When matrix size is more than 10 5, the number of computations also increased to 3.3 times, and the elapsed time of DD-SpMV in BCRS4×1 can be about 45% of that in CRS format.

High precision arithmetic can improve the convergence of Krylov subspace methods; however, it is very costly. One system of high precision arithmetic is Double-Double arithmetic, which uses two double precision variables to implement one quadruple precision variable. We accelerated double sparse matrix in BCRS format and DD vector product (DD-SpMV) using AVX2. DD-SpMV in CRS format using AVX2 needs fraction processing each row. BCRS format which aligns the SIMD register's length can eliminate fraction processing and improve memory access. However, it may increase operations. In this paper, we have shown that trade-off between increased operations and eliminated fraction processing and improving memory access. In experimental results, we concluded that the best BCRS block size is BCRS4×1. The effect of improving memory access in BCRS format depends on matrix sizes. When matrix size is more than 10 5, the number of computations also increased to 3.3 times, and the elapsed time of DD-SpMV in BCRS4×1 can be about 45% of that in CRS format.

収録刊行物

  • 情報処理学会論文誌コンピューティングシステム(ACS)

    情報処理学会論文誌コンピューティングシステム(ACS) 7(4), 25-33, 2014-12-16

    一般社団法人情報処理学会

各種コード

  • NII論文ID(NAID)
    110009851548
  • NII書誌ID(NCID)
    AA11833852
  • 本文言語コード
    JPN
  • 資料種別
    Article
  • ISSN
    1882-7829
  • データ提供元
    NII-ELS  IPSJ 
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