A Dependability Selection Method for Multicore Processors Considering Power-performance Trade-off

• Sato, Toshinori

  Kyushu University | JST, CREST

• Funaki, Toshimasa

  Kyushu Institute of Technology

Bibliographic Information

Other Title

• マルチコアプロセッサのための電力・性能間トレードオフを考慮したディペンダビリティ選択法
• マルチコアプロセッサ ノ タメ ノ デンリョク ・ セイノウ カン トレードオフ オ コウリョ シタ ディペンダビリティ センタクホウ

Abstract

As deep submicron technologies are advanced, we face new challenges, such as power consumption and soft errors. A naive technique, which utilizes emerging multicore processors and relies upon thread-level redundancy to detect soft errors, is power hungry. Another technique, which relies upon instruction-level redundancy, seriously diminishes computing performance. This paper investigates a trade-off between power and performance of a dependable multicore processor, which is named multiple clustered core processor (MCCP). It is proposed to hybrid thread- and instruction-level redundancy in order to achieve both high power efficiency and small performance loss. Detailed simulations show that the MCCP exploiting the hybrid technique improves power efficiency in energy-delay product by 13% when it compares with the one exploiting the naive thread-level technique.

Journal

• 情報処理学会論文誌

  情報処理学会論文誌 49 (6), 2005-2015, 2008-06-15

  情報処理学会

Keywords

• ディペンダブル情報処理
• 計算機アーキテクチャ

Details

• CRID: 1050017057729347072
• NII Article ID: 120000980426
• NII Article ID: 10026769021
• NII Book ID: AN00116647
• ISSN: 18827764
• ISSN: 18827837
• ISSN: 03875806
• HANDLE: 2324/10747
• NDL BIB ID: 024275830
• Web Site: http://id.nii.ac.jp/1001/00009554/
• Web Site: http://id.ndl.go.jp/bib/024275830
• Web Site: https://ndlsearch.ndl.go.jp/books/R000000004-I024275830
• Text Lang: ja
• Article Type: journal article
• Data Source:
  • IRDB
  • NDL
  • CiNii Articles
  • KAKEN