A New Design Approach for High-Throughput Arithmetic Circuits for Single-Flux-Quantum Microprocessors

• Tanaka, M.

• Yamanashi, Y.

• Kamiya, Y.

• Akimoto, A.

• Irie, N.

• Park, H.

• Fujimaki, A.

• Yoshikawa, N.

• Terai, H.

• Yorozu, S.

抄録

We propose a new design approach for high-throughput arithmetic circuits based on state transitions using single-flux-quantum (SFQ) logic circuits. Microprocessors have several complex interconnects in datapath including loops of data, to which only one SFQ pulse is allowed to be confined, and the loops can spoil the high-throughput nature of SFQ circuits. In our new approach, we regard an arithmetic circuit with loops as a sequential logic circuit, and we use nondestructive readout gates (NDROs) as storage elements of the internal state. We can eliminate the loops and achieve high throughput by translating calculations into transitions of the state stored in the NDROs. We have implemented a bit-serial adder with the proposed approach, and demonstrated 36-GHz operations using the niobium 2.5-kA/cm(2) standard process technology.

収録刊行物

• IEEE transactions on applied superconductivity

  IEEE transactions on applied superconductivity 17 (2, Part 1), 516-519, 2007-06

  Institute of Electrical and Electronics Engineers

キーワード

• arithmetic circuits
• high throughput
• microprocessor
• single flux quantum (SFQ) logic

詳細情報

• CRID: 1050282812715825024
• NII論文ID: 120001723312
• NII書誌ID: AA10791666
• ISSN: 10518223
• Web Site: http://hdl.handle.net/10131/4227
• 本文言語コード: en
• 資料種別: journal article
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