Recent progress in integration of III-V nanowire transistors on Si substrate by selective-area growth

• Tomioka, Katsuhiro

• Fukui, Takashi

抄録

We report on the recent progress in electronic applications using III-V nanowires (NWs) on Si substrates using the selective-area growth method. This method could align vertical III-V NWs on Si under specific growth conditions. Detailed studies of the III-V NW/Si heterointerface showed the possibility of achieving coherent growth regardless of misfit dislocations in the III-V/Si heterojunction. The vertical III-V NWs grown using selective-area growth were utilized for high performance vertical field-effect transistors (FETs). Furthermore, III-V NW/Si heterointerfaces with fewer misfit dislocations provided us with a unique band discontinuity with a new functionality that can be used for the application of tunnel diodes and tunnel FETs. These demonstrations could open the door to a new approach for creating low power switches using III-V NWs as building-blocks of future nanometre-scaled electronic circuits on Si platforms.

収録刊行物

• Journal of Physics D: Applied Physics

  Journal of Physics D: Applied Physics 47 (39), 394001-, 2014-10-01

  IOP Publishing

キーワード

• III-V nanowires
• epitaxy
• FET
• tunnel FET

詳細情報

• CRID: 1050001202675073664
• NII論文ID: 120005512025
• HANDLE: 2115/57448
• ISSN: 00223727
• 本文言語コード: en
• 資料種別: journal article
• データソース種別:
  • IRDB
  • CiNii Articles