ジッタシェーピング型ΔΣDACと試作

• 渡邉 裕紀

書誌事項

タイトル別名

• DELTA-SIGMA DAC WITH JITTER-SHAPER AND PROTOTYPE

抄録

type:Article

We present a novel delta-sigma digital-to-analog converter (DSDAC) using a jitter shaper to augment the noise caused by clock jitter. The jitter shaper is designed for a 0.18 μm CMOS and comprises switched capacitor and sample-and-hold circuits. We simulate the DSDAC in MATLAB/simulink and design and simulate the complete jitter shaper circuit in Virtuoso/spector. We predict that the jitter shaper will improve the signal-to-noise ratio (SNR). We had the A to the integrated circuit and measured the DSDAC combined with FPGA.

収録刊行物

• 法政大学大学院紀要. 理工学・工学研究科編

  法政大学大学院紀要. 理工学・工学研究科編 57 1-8, 2016-03-24

  法政大学大学院理工学・工学研究科

キーワード

• D/A converter
• delta-sigma modulator
• jitter shaper
• clock jitter
• IC

詳細情報

• CRID: 1390009224830895872
• NII論文ID: 120005771143
• NII書誌ID: AA12677220
• ISSN: 21879923
• DOI: 10.15002/00013083
• Web Site: http://hdl.handle.net/10114/12421
• 本文言語コード: ja
• データソース種別:
  • JaLC
  • IRDB
  • CiNii Articles