Performance Optimization for Low-Leakage Caches based on Sleep-Line Access Density

• 小宮, 礼子

  福岡大学大学院工学研究科電子情報工学専攻

• 井上, 弘士

  科学技術振興機構

• 村上, 和彰

  財団法人九州システム情報技術研究所 | 九州大学大学院システム情報科学研究院情報理学部門

抄録

As the transistor feature sizes and threshold voltages reduce, leakage energy consumption has become an inevitable issue for high-performance microprocessor designs. In order to solve the energy issue, a number of techniques to reduce the cache leakage energy have so far been proposed. However, the low-leakage caches affect negatively the processor performance due to the accesses to non-state-preserving sleep-mode lines. In this paper, we analyze the access behavior on a low-leakage cache and show a remarkable observation for the density of sleep-line accesses. Based on this observation, we propose a new cache management technique to alleviate the performance degradation caused by low-leakage caches. In our approach, a small number of cache lines which are frequently accessed in the sleep mode are forced to stay in always-active mode. Although this mode is high leakage, it saves the state. Thus, the performance overhead caused by the leakage optimization can be eliminated.

4th Workshop on Optimizations for DSP and Embedded Systems : March 26, 2006 : Manhattan, New York, NY

収録刊行物

• Workshop on Optimizations for DSP and Embedded Systems

  Workshop on Optimizations for DSP and Embedded Systems 4 2006-03-26

キーワード

• High performance
• Low leakage
• Cache

詳細情報

• CRID: 1050017057729261184
• NII論文ID: 120006654345
• HANDLE: 2324/11885
• 本文言語コード: en
• 資料種別: conference paper
• データソース種別:
  • IRDB
  • CiNii Articles