Practical test architecture optimization for system-on-a-chip under floorplanning constraints

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Abstract

In testing system-on-a-chip (SOC), external pins for test are getting more and more precious hardware resources because the number of external pins is strongly restricted. Cores, which are basic components to build SOCs, are tested via test access mechanisms (TAMs) such as a test bus architecture. When cores are tested via TAMs, test stimuli and test responses for cores have to be transported over these TAMs. There is often the difference between the numbers of input/output ports of cores and the widths of TAMs. This difference causes the serialization of test patterns. It is probable that some parts of TAMs are unused because of the difference. This is a wasteful usage of TAMs. Test scheduling should be done in order to remove such a wasteful usage of TAMs. In this paper, a novel and practical test architecture optimization is proposed such that test time is minimized with floorplanning constraints abided. In this proposal, the computation time for the optimization can be alleviated by floorplanning manipulation. Several experimental results to this optimization are shown to validate this proposal using a commercial LP solver.

Journal

  • IEEE Computer Society Symposium on VLSI

    IEEE Computer Society Symposium on VLSI, 179-184, 2004-02

    IEEE Computer Society

Codes

  • NII Article ID (NAID)
    120006655286
  • Text Lang
    ENG
  • Article Type
    conference paper
  • Data Source
    IR 
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