A Low Power I-Cache Design with Tag-Comparison Reuse
-
- Inoue, Koji
- Dept. of Elec. Eng. and Computer Science Fukuoka University
-
- Tanaka, Hidekazu
- Dept. of Elec. Eng. and Computer Science Fukuoka University
-
- Moshnyaga, Vasily G.
- Dept. of Elec. Eng. and Computer Science Fukuoka University
-
- Murakami, Kazuaki
- Dept. of Informatics Kyushu University
Abstract
This paper reports design and evaluation results of a low-energy I-cache architecture, called history-based tagcomparison (HBTC) cache. The HBTC cache attempts to re-use tag-comparison results to detect and eliminate unnecessary memory-array activations. We have performed cycle accurate simulations, and have designed an SRAM core based on a 0.18 $ mu m $ CMOS technology. As a result, it has been observed that the HBTC approach can achieve 60% of energy reduction, with only 0.3% performance degradation, compared to a conventional cache. Furthermore, we have also evaluated the potential of the HBTC cache by combining with other low-energy techniques.
Journal
-
- Proc. of the The International Symposium on System-On-Chip (SOC04)
-
Proc. of the The International Symposium on System-On-Chip (SOC04) 61-67, 2004-11
IEEE