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Abstract

This paper investigates a possible architecture to a dynamically adaptable processor. In this architecture, the running application is profiled and dynamic traces of high frequently executed loops (hot paths) are detected. The proposed online profiling methodology is mainly hardware-based so that overhead can be reduced as much as possible. Studying the behavior of branch and jump instructions, gathered by the profiler, guides us to the hot paths. To improve the performance for the next iterations, hot paths are optimized using dynamic software pipelining technique, which seems a suitable method for our simplified 8- way VLIW accelerator. To exploit the hardware accelerator, the binary code is rewritten. Some preliminary performance evaluations show speedup.

Journal

  • The Proceedings of the 11th International CSI Conference

    The Proceedings of the 11th International CSI Conference, 520-523, 2006-01

    Computer Society of Iran

Codes

  • NII Article ID (NAID)
    120006655347
  • Text Lang
    ENG
  • Article Type
    conference paper
  • Data Source
    IR 
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