Power-Performance Trade-off of a Dependable Multicore Processor
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- Sato, Toshinori
- System LSI Research Center, Kyushu University
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- Funaki, Toshimasa
- Graduate School of Computer Science and System Engineering, Kyushu Institute of Technology
Abstract
As deep submicron technologies are advanced, new challenges, such as power consumption and soft errors, are emerging. A naive technique, which utilizes emerging multicore processors and relies upon thread-level redundancy to detect soft errors, is power hungry. Another technique, which relies upon instruction-level redundancy, diminishes computing performance seriously. This paper investigates trade-off between power and performance of a dependable multicore processor, which is named multiple clustered core processor (MCCP). It is proposed to hybrid thread- and instruction-level redundancy to achieve both large power efficiency and small performance loss. Detailed simulations show that the MCCP exploiting the hybrid technique improves power efficiency in energy-delay product by 13% when it is compared with the one exploiting the naive thread-level technique.
The 13th Pacific Rim International Symposium on Dependable Computing : December 17-19, 2007 : Australia
Journal
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- Proceedings of the 13th Pacific Rim International Symposium on Dependable Computing
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Proceedings of the 13th Pacific Rim International Symposium on Dependable Computing 268-273, 2007-12
