Instruction Scheduling for Variation-originated Variable Latencies
抄録
The advance in semiconductor technologies presents the serious problem of parameter variations. The affect threshold voltage of transistors and thus circuit delay also has variations. Recently, variable latency adders and long latency adders are proposed to manage the variation problem. Unfortunately, replacement of variation-affected adder with the long latency ones has severe impact on processor performance. In order to maintain performance, this paper proposes an instruction scheduling technique considering instruction criticality. By issuing and executing only uncritical instructions in the long latency ALU, we can maintain processor performance. From detailed simulations, we find that the proposed scheduling technique improves processor performance by 12.5% on average over the conventional scheduling, and performance degradation from a variation-free processor is only 4.0% on average when 2 of 4 ALU’s are affected by variations.
the 9th International Symposium on Quality Electronic Design (ISQED'08) : March 17-19, 2008 : San Jose, CA, USA
収録刊行物
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- 9th International Symposium on Quality Electronic Design
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9th International Symposium on Quality Electronic Design 361-364, 2008-03-18
