Deep pipelined one-chip FPGA implementation of a real-time image-based human detection algorithm

• Negi, Kazuhiro

• Dohi, Keisuke

• Shibata, Yuichiro

• Oguri, Kiyoshi

Abstract

In this paper, deep pipelined FPGA implementation of a real-time image-based human detection algorithm is presented. By using binary patterned HOG features, AdaBoost classifiers generated by offline training, and some approximation arithmetic strategies, our architecture can be efficiently fitted on a low-end FPGA without any external memory modules. Empirical evaluation reveals that our system achieves 62.5 fps of the detection throughput, showing 96.6% and 20.7% of the detection rate and the false positive rate, respectively. Moreover, if a highspeed camera device is available, the maximum throughput of 112 fps is expected to be accomplished, which is 7.5 times faster than software implementation.

2011 International Conference on Field-Programmable Technology, FPT 2011, Article number6132679; 2011

Journal

• 2011 International Conference on Field-Programmable Technology, FPT 2011

  2011 International Conference on Field-Programmable Technology, FPT 2011 6132679-, 2011-12

  IEEE

Keywords

• Detection rates
• Empirical evaluations
• External memory
• False positive rates
• FPGA implementations
• Human detection
• Image-based
• Maximum through-put
• Off-line training
• Software implementation

Details

• CRID: 1050855522098742784
• NII Article ID: 120006985646
• HANDLE: 10069/29887
• Web Site: https://nagasaki-u.repo.nii.ac.jp/records/9292
• Text Lang: en
• Article Type: conference paper
• Data Source:
  • IRDB
  • CiNii Articles