書誌事項
- タイトル別名
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- A hardware-oriented echo state network and its FPGA implementation
抄録
This paper proposes implementation of an Echo State Network (ESN) to Field Programmable Gate Array (FPGA). The proposed method is able to reduce hardware resources by using fixed-point operation, quantization of weights, which includes accumulate operations and efficient dataflow modules. The performance of the designed circuit is verified via experiments including prediction of sine and cosine waves. Experimental result shows that the proposed circuit supports to 200 MHz of operation frequency and facilitates faster computing of the ESN algorithm compared with a central processing unit.
収録刊行物
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- Journal of Robotics, Networking and Artificial Life
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Journal of Robotics, Networking and Artificial Life 7 (1), 58-62, 2020-05-18
Atlantis Press
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詳細情報 詳細情報について
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- CRID
- 1050851087328422272
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- NII論文ID
- 120007035846
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- ISSN
- 24059021
- 23526386
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- HANDLE
- 10228/00008260
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- 本文言語コード
- en
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- 資料種別
- journal article
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- データソース種別
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