A Circuit Analysis of Pre-Emphasis Pulses for RC Delay Lines

• MATSUYAMA Kazuki

  Shizuoka University

• TANZAWA Toru

  Shizuoka University

抄録

This paper formulates minimal word-line (WL) delay time with pre-emphasis pulses to design the pulse width as a function of the overdrive voltage for large memory arrays such as 3D NAND. Circuit theory for a single RC line only with capacitance to ground and that only with coupling capacitance as well as a general case where RC lines have both grounded and coupling capacitance is discussed to provide an optimum pre-emphasis pulse width to minimize the delay time. The theory is expanded to include the cases where the resistance of the RC line driver is not negligibly small. The minimum delay time formulas of a single RC delay line and capacitive coupling RC lines was in good agreement (i.e. within 5% error) with measurement. With this research, circuit designers can estimate an optimum pre-emphasis pulse width and the delay time for an RC line in the initial design phase.

収録刊行物

• IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences

  IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences E104.A (6), 912-926, 2021-06-01

  一般社団法人 電子情報通信学会

キーワード

• pre-emphasis
• RC delay
• delay time
• NAND flash
• flat panel display
• word-line
• column-line

詳細情報

• CRID: 1390569690549815296
• NII論文ID: 130008046396
• DOI: 10.1587/transfun.2020eap1083
• ISSN: 17451337
• ISSN: 09168508
• HANDLE: 10297/00028229
• Web Site: https://shizuoka.repo.nii.ac.jp/records/13310
• Web Site: https://www.jstage.jst.go.jp/article/transfun/E104.A/6/E104.A_2020EAP1083/_pdf
• 本文言語コード: en
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