Differential Signal Balancer Embedded in Silicon LSI with Bifilar Coupling Inductors and Stacked Delay Lines

• Kameya, Masaaki

• 御福, 英史

• 中村, 和之

抄録

The differential signal balancer, a new principle common mode filter that uses a delay line technology, is embedded in the metal wiring layer of silicon LSI with a small area of 100 μm by 230 μm. To increase the capability of the common mode noise reduction, a series resistance in the internal inductor is reduced by configured with bifilar winding. The noise reduction capability is verified in the circuit simulation including the influences of the ESD diode.

2021 International Conference on Solid State Devices and Materials (SSDM2021), September 6–9, 2021, ALL-VIRTUAL conference

詳細情報

• CRID: 1050292572092982144
• NII論文ID: 120007149029
• HANDLE: 10228/00008469
• Web Site: https://kyutech.repo.nii.ac.jp/records/7265
• 本文言語コード: en
• 資料種別: conference paper
• データソース種別:
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  • CiNii Articles