Evaluation of capacitance-voltage characteristics for high voltage SiC-JFET

• Funaki Tsuyoshi

  Kyoto University, Dept. of Electrical Eng.

• Kimoto Tsunenobu

  Kyoto University, Dept. of Electronic Science and Eng., Graduate school of Engineering

• Hikihara Takashi

  Kyoto University, Dept. of Electrical Eng.

抄録

Capacitance between terminals of a power semiconductor device substantially affects on its switching operation. This paper presents a capacitance-voltage (C-V) characterization system for measuring high voltage SiC-JFET and the results. The C-V characterization system enables one to impose high drain-source voltage to the device and extracts the capacitance between two of three terminals in FET by eliminating its influence on the neighboring terminal. The capacitance between the gate and drain, and the drain and source represents the hybrid structure of the lateral channel and vertical drift layer of the SiC-JFET.

収録刊行物

• IEICE Electronics Express

  IEICE Electronics Express 4 (16), 517-523, 2007

  一般社団法人 電子情報通信学会

キーワード

• C-V characteristics
• high voltage
• SiC
• JFET
• device structure

詳細情報

• CRID: 1390001205213259904
• NII論文ID: 130000088441
• DOI: 10.1587/elex.4.517
• ISSN: 13492543
• Web Site: http://www.jstage.jst.go.jp/article/elex/4/16/4_16_517/_pdf
• 本文言語コード: en
• データソース種別:
  • JaLC
  • Crossref
  • CiNii Articles
• 抄録ライセンスフラグ: 使用不可