A Behavioral Synthesis System for Asynchronous Circuits with Bundled-data Implementation

• Hamada Naohiro

  The University of Aizu

• Shiga Yuki

  The University of Aizu

• Konishi Takao

  The University of Aizu

• Saito Hiroshi

  The University of Aizu

• Yoneda Tomohiro

  National Institute of Informatics

• Myers Chris

  The University of Utah

• Nanya Takashi

  The University of Tokyo

抄録

This paper proposes a behavioral synthesis system for asynchronous circuits with bundled-data implementation. The proposed system is based on a behavioral synthesis method for synchronous circuits and extended on operation scheduling and control synthesis for bundled-data implementation. The proposed system synthesizes an RTL model and a simulation model from a behavioral description specified by a restricted C language, a resource library, and a set of design constraints. This paper shows the effectiveness of the proposed system in terms of area and latency through comparisons among bundled-data implementations synthesized by the proposed system, synchronous counterparts, and bundled-data implementations synthesized by using a behavioral synthesis method for synchronous circuits directly.

収録刊行物

• Information and Media Technologies

  Information and Media Technologies 4 (2), 211-226, 2009

  Information and Media Technologies 編集運営会議

詳細情報

• CRID: 1390282680240911360
• NII論文ID: 130000120666
• DOI: 10.11185/imt.4.211
• ISSN: 18810896
• 本文言語コード: en
• データソース種別:
  • JaLC
  • CiNii Articles
• 抄録ライセンスフラグ: 使用不可