Design of fast digit-serial adders using SFQ logic circuits

DOI Web Site 被引用文献3件 参考文献7件
  • Park Heejoung
    Department of Electrical and Computer Engineering, Yokohama National University
  • Yamanashi Yuki
    Department of Electrical and Computer Engineering, Yokohama National University
  • Yoshikawa Nobuyuki
    Department of Electrical and Computer Engineering, Yokohama National University
  • Tanaka Masamitsu
    Department of Information Engineering, Nagoya University
  • Fujimaki Akira
    Department of Quantum Engineering, Nagoya University

抄録

We propose an algorithm of digit-serial adders using single-flux-quantum (SFQ) circuits. The proposed digit-serial adder adapts the carry look-ahead (CLA) adder architecture to generate carry signals, which are generated from the digit-serial data and fed back internally to the following digit-serial data to increase the throughput of the calculation. We have designed and implemented a 4-bit digit-serial adder using the SRL 2.5kA/cm2 niobium standard process to demonstrate its high-speed operation. The total number of Josephson junctions is 2316. We have successfully tested full operations of the 4-bit digit-serial adder with a bias margin of ± 15% at 25GHz. Its maximum operation frequency was 30GHz.

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