A 14.3% PAE parallel class-A and AB 60GHz CMOS PA

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  • Li Ning
    Department of Physical Electronics, Tokyo Institute of Technology
  • Matsushita Kota
    Department of Physical Electronics, Tokyo Institute of Technology
  • Okada Kenichi
    Department of Physical Electronics, Tokyo Institute of Technology
  • Matsuzawa Akira
    Department of Physical Electronics, Tokyo Institute of Technology

抄録

At 60GHz, it becomes difficult to achieve a high power added efficiency (PAE) and large output power for CMOS power amplifier (PA). A parallel class-A and AB pseudo Doherty PA is designed in CMOS 65nm process to obtain a high PAE and large output power. The PA achieves a 9.8-dB gain at 60GHz. The measured large signal results show that a maximum power added efficiency (PAE) of 14.3% and 12.0% at 1dB compression point are realized. The chip consumes 45∼58mW power from a 1.2-V supply voltage. The chip area is 0.6mm2 including pads.

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