A third order delta-sigma modulator employing shared opamp technique for WCDMA on 0.18um CMOS

• Fahmy Ghazal

  Graduate School of Information Science and Electrical Engineering, Kyushu University

• Kanemoto Daisuke

  Graduate School of Information Science and Electrical Engineering, Kyushu University

• Kanaya Haruichi

  Graduate School of Information Science and Electrical Engineering, Kyushu University

• Yoshida Keiji

  Graduate School of Information Science and Electrical Engineering, Kyushu University

• Pokharel Ramesh

  EJUST Center, Kyushu University

• Anand Awinash

  Graduate School of Information Science and Electrical Engineering, Kyushu University

Abstract

Analog to digital converter is a vital component in a wireless transceiver. High order loop filter is one of conventional approach to attain high resolution delta-sigma modulator which required one opamp for each integrator. A third orders delta-sigma modulator (DSM) has been designed utilizing shared opamp technique to reduce number of opamp required and decrease power consumption. Moreover, this architecture has relaxed comparator speed which is appropriate for wireless applications. First and second stages are sharing one opamp in integration and sampling phase. The proposed circuit has been designed on TSMC 0.18um CMOS technology. 2MHz Bandwidth, 50dB Peak SQNR, which is suitable for WCDMA, have been achieved.

Journal

• IEICE Electronics Express

  IEICE Electronics Express 8 (15), 1204-1209, 2011

  The Institute of Electronics, Information and Communication Engineers

Keywords

• delta-sigma modulator
• time sharing
• low power consumption

Details

• CRID: 1390001205214547968
• NII Article ID: 130000959509
• DOI: 10.1587/elex.8.1204
• ISSN: 13492543
• Web Site: http://www.jstage.jst.go.jp/article/elex/8/15/8_15_1204/_pdf
• Text Lang: en
• Data Source:
  • JaLC
  • Crossref
  • CiNii Articles
  • KAKEN
• Abstract License Flag: Disallowed