A case for routing cache on HPC switches

• Ishida Shin-ichi

  Graduate School of Science and Technology, Keio University

• Koibuchi Michihiro

  National Institute of Informatics

• Nishi Hiroaki

  Graduate School of Science and Technology, Keio University National Institute of Informatics

Abstract

Large many-core parallel applications become sensitive to communication latencies, suggesting the need for low-latency networks in high-performance computing systems. Switch delay dominates network latencies. To reduce the network latencies, we exploit routing cache on a switch. Routing decision based on off-chip CAM (Content Addressable Memory)-based table lookup imposes a significant delay, however, using on-chip small routing cache can bypass it when it hits. Our simulation results show that the only 256-entry routing cache hits 98% on over 4k-host systems with the matrix-transpose traffic, and the 1024-entry routing cache improves not only up to 16% of packet latency but also up to 18% of network throughput.

Journal

• IEICE Communications Express

  IEICE Communications Express 1 (1), 49-53, 2012

  The Institute of Electronics, Information and Communication Engineers

Keywords

• switch architecture
• interconnection networks
• high performance computing

Details

• CRID: 1390282680392783232
• NII Article ID: 130001921491
• DOI: 10.1587/comex.1.49
• ISSN: 21870136
• Web Site: https://www.jstage.jst.go.jp/article/comex/1/1/1_49/_pdf
• Text Lang: en
• Data Source:
  • JaLC
  • Crossref
  • CiNii Articles
• Abstract License Flag: Disallowed