Design of the ultra low-power synchronizer using ADCL buffer for adiabatic logic

• Cho Seung-Il

  Graduate School of Science and Engineering, Yamagata University

• Harada Tomochika

  Graduate School of Science and Engineering, Yamagata University

• Yokoyama Michio

  Graduate School of Science and Engineering, Yamagata University

抄録

The adiabatic dynamic CMOS logic (ADCL) has been studied to reduce the power dissipation in conventional CMOS logic. The clock signal of logic circuits should be synchronized with the AC power source to maintain adiabatic charging/discharging with low power for the ADCL. In this paper, an ultra low-power synchronizer using ADCL buffer is proposed. The ADCL buffer has been designed using features of automatic synchronization between AC signal and output of gate stage. Power consumptions of the proposed ADCL synchronizer are found to be 99.4nW at best case and 109.8nW at worst case, when AC signal and clock frequencies are 110MHz and 10MHz, respectively.

収録刊行物

• IEICE Electronics Express

  IEICE Electronics Express 9 (20), 1576-1585, 2012

  一般社団法人 電子情報通信学会

キーワード

• synchronization
• adiabatic dynamic CMOS logic (ADCL)
• low power
• ADCL buffer

詳細情報

• CRID: 1390001205214739584
• NII論文ID: 130001922111
• DOI: 10.1587/elex.9.1576
• ISSN: 13492543
• Web Site: https://www.jstage.jst.go.jp/article/elex/9/20/9_1576/_pdf
• 本文言語コード: en
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