Accurate Estimation of the Worst-case Delay in Statistical Static Timing Analysis

DOI
  • Terada Haruhiko
    Department of Communications and Computer Engineering, Kyoto University
  • Fukuoka Takayuki
    Department of Communications and Computer Engineering, Kyoto University
  • Tsuchiya Akira
    Department of Communications and Computer Engineering, Kyoto University
  • Onodera Hidetoshi
    Department of Communications and Computer Engineering, Kyoto University

Abstract

In this paper, we propose an approximation method for the statistical MAX operation such that it results in a normal distribution good for the worst-case delay analysis. The important operation in SSTA is SUM and MAX of distributions. In general, the delay variation is modeled as normal distribution. The result of SUM operation of two normal distributions is also normal distribution. On the other hand, the result of MAX operation is not normal distribution. Thus approximation to normal distribution is commonly used. We also explain that the proposed MAX operation at each gate also contributes to the accurate estimation in the worst-case delay analysis of the whole circuit. Experimental results show that the proposed method leads to a good approximation for a normal distribution resulted from MAX operation of normal distributions with and without correlation, and the approximation improves the accuracy of the worst-case delay analysis. In a circuit example, the errors of worst-case delay computed by the previous method are about 20%, and the errors computed by the proposed method are under 5%.

Journal

Details 詳細情報について

  • CRID
    1390282680242454016
  • NII Article ID
    130002073186
  • DOI
    10.11185/imt.3.729
  • ISSN
    18810896
  • Text Lang
    en
  • Data Source
    • JaLC
    • CiNii Articles
  • Abstract License Flag
    Disallowed

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