Embedded System Covalidation with RTOS Model and FPGA

• Shibata Seiya

  Graduate School of Information Science, Nagoya University

• Honda Shinya

  Graduate School of Information Science, Nagoya University

• Hara Yuko

  Graduate School of Information Science, Nagoya University

• Tomiyama Hiroyuki

  Graduate School of Information Science, Nagoya University

• Takada Hiroaki

  Graduate School of Information Science, Nagoya University

Abstract

This paper presents a software/hardware covalidation environment for embedded systems. Our covalidation environment consists of a simulation model of RTOS which fully supports services of ITRON, multiple hardware simulators, FPGA and a covalidation backplane. All of the simulators are executed concurrently with communication. The RTOS model can be executed on the host computer natively, therefore the software can be simulated much faster than on an instruction set simulator. FPGA can execute the hardware much faster than HDL simulators. With the RTOS model and FPGA, both application software and hardware can be validated in a short time. In the experiment, with using our covalidation environment, we perform covalidation of an MPEG4 decoder system and show the effectiveness of the covalidation environment.

Journal

• Information and Media Technologies

  Information and Media Technologies 3 (4), 739-743, 2008

  Information and Media Technologies Editorial Board

Details

• CRID: 1390001205265742592
• NII Article ID: 130002073187
• DOI: 10.11185/imt.3.739
• ISSN: 18810896
• Text Lang: en
• Data Source:
  • JaLC
  • CiNii Articles
• Abstract License Flag: Disallowed