Platform and Mapping Methodology for Heterogeneous Multicore Processors

• HARIYAMA Masanori

  Graduate School of Information Sciences, Tohoku University

• WAIDYASOORIYA Hasitha Muthumala

  Graduate School of Information Sciences, Tohoku University

• TAKEI Yasuhiro

  Graduate School of Information Sciences, Tohoku University

• KAMEYAMA Michitaka

  Graduate School of Information Sciences, Tohoku University

Abstract

Heterogeneous multi-core processors are attracted by various type of applications from low-power media applications to high-performance computing due to their capability of drawing strengths of different cores to improve the overall performance. However, the data transfer bottlenecks between different cores becomes a serious problem. This paper presents two key methodologies to solve the data transfer bottoleneck: memory allocation considering a addressing function constraint and task allocation based on algorithm transformation. Moreover, in order to help to explore accelerator architecture suitable for applications, this paper presents a platform based on FPGAs where circuity is reconfigured by users after fabrication.

Journal

• Interdisciplinary Information Sciences

  Interdisciplinary Information Sciences 18 (2), 175-184, 2012

  The Editorial Committee of the Interdisciplinary Information Sciences

Keywords

• heterogeneous multi-core processor
• reconfigurable architecture
• dynamic reconfiguration
• task-allocation
• memory allocation

Details

• CRID: 1390001204436404480
• NII Article ID: 130002531678
• NII Article ID: 120005428604
• DOI: 10.4036/iis.2012.175
• ISSN: 13476157
• ISSN: 13409050
• HANDLE: 10097/57183
• Web Site: https://tohoku.repo.nii.ac.jp/records/41841
• Text Lang: en
• Data Source:
  • JaLC
  • IRDB
  • Crossref
  • CiNii Articles
  • KAKEN
• Abstract License Flag: Disallowed