Design methodology for determining the number of stages in a cascaded time amplifier to minimize area consumption

• Niitsu Kiichi

  Department of Electrical Engineering and Computer Science, Graduate School of Engineering, Nagoya University

• Harigai Naohiro

  Division of Electronics and Informatics, Faculty of Science and Technology, Gunma University

• Kobayashi Haruo

  Division of Electronics and Informatics, Faculty of Science and Technology, Gunma University

Abstract

This paper describes a design methodology for determining the number of stages in a cascaded time amplifier to minimize the area consumption. The total area consumption is categorized into three parts, which allows mathematical analysis and optimization to be performed. A combination of the proposed mathematical analysis and 2D mapping can determine the number of stages to minimize the area consumption.

Journal

• IEICE Electronics Express

  IEICE Electronics Express 10 (11), 20130289-20130289, 2013

  The Institute of Electronics, Information and Communication Engineers

Keywords

• time amplifier
• CMOS
• integrated circuits
• design methodology
• design for testability

Details

• CRID: 1390001205214545920
• NII Article ID: 130003364875
• DOI: 10.1587/elex.10.20130289
• ISSN: 13492543
• Web Site: https://www.jstage.jst.go.jp/article/elex/10/11/10_10.20130289/_pdf
• Text Lang: en
• Data Source:
  • JaLC
  • Crossref
  • CiNii Articles
  • KAKEN
• Abstract License Flag: Disallowed