A Prototype System for Many-Core Architecture SMYLEref with FPGA Evaluation Boards

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  • NGUYEN Son-Truong
    Graduate School of Information Systems, The University of Electro-Communications
  • KONDO Masaaki
    Graduate School of Information Systems, The University of Electro-Communications
  • HIRAO Tomoya
    Graduate School of Information Science and Electrical Engineering, Kyushu University
  • INOUE Koji
    Graduate School of Information Science and Electrical Engineering, Kyushu University

Abstract

Nowadays, the trend of developing micro-processor with hundreds of cores brings a promising prospect for embedded systems. Realizing a high performance and low power many-core processor is becoming a primary technical challenge. Generally, three major issues required to be resolved includes: 1) realizing efficient massively parallel processing, 2) reducing dynamic power consumption, and 3) improving software productivity. To deal with these issues, we propose a solution to use many low-performance but small and very low-power cores to obtain very high performance, and develop a referential many-core architecture and a program development environment. This paper introduces a many-core architecture named SMYLEref and its prototype system with off-the-shelf FPGA evaluation boards. The initial evaluation results of several SPLASH2 benchmark programs conducted on our developed 128-core platform are also presented and discussed in this paper.

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