A LUT manipulation based intrinsic evolvable system

• Zhang Kaifeng

  ATR Key Lab, National University of Defense Technology

• Lu Huanzhang

  ATR Key Lab, National University of Defense Technology

• Hu Weidong

  ATR Key Lab, National University of Defense Technology

• Wang Jian

  ATR Key Lab, National University of Defense Technology

抄録

The paper presents an evolvable system for intrinsic hardware evolution based on look-up-table (LUT) manipulation. We also introduce dynamic routing using multiplexer to improve the flexibility of the system. The proposed approach is implemented on Xilinx ML403 Evaluation Platform, and an evolution of 3-bit multiplier is employed for verification. The experimental results show that more than three orders of evolution speed enhancement over JBits and one order of evolution speed enhancement over bitstream reverse engineering (BRE) based methods is achieved.

収録刊行物

• IEICE Electronics Express

  IEICE Electronics Express 11 (4), 20131003-20131003, 2014

  一般社団法人 電子情報通信学会

キーワード

• evolvable hardware
• LUT
• virtual reconfigurable circuits
• bitstream reverse engineering

詳細情報

• CRID: 1390001205212145280
• NII論文ID: 130003392262
• DOI: 10.1587/elex.11.20131003
• ISSN: 13492543
• Web Site: https://www.jstage.jst.go.jp/article/elex/11/4/11_11.20131003/_pdf
• 本文言語コード: en
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