A low-offset cascaded time amplifier with reconfigurable inter-stage connection

• Niitsu Kiichi

  Graduate School of Engineering, Nagoya University

• Harigai Naohiro

  Division of Electronics and Infomatics, Gunma University

• Yamaguchi Takahiro J.

  Advantest Laboratories Ltd.

• Kobayashi Haruo

  Division of Electronics and Infomatics, Gunma University

Abstract

This study demonstrates the design and testing of a reconfigurable cascaded time amplifier (TA) that enables a reduction in the output offset. By testing the polarity of the output offset time caused by process variations in each stage and then reconfiguring the inter-stage connections, we find that the total output offset time can be reduced dramatically. The results of a SPICE simulation of a 65-nm CMOS match well with the theoretical estimates and show the effectiveness of this proposed testing structure and reconfigurable inter-stage connection technique.

Journal

• IEICE Electronics Express

  IEICE Electronics Express 11 (10), 20140203-20140203, 2014

  The Institute of Electronics, Information and Communication Engineers

Keywords

• time amplifier
• jitter measurement
• design for testability
• BIST

Details

• CRID: 1390001205214127616
• NII Article ID: 130003392309
• DOI: 10.1587/elex.11.20140203
• ISSN: 13492543
• Web Site: https://www.jstage.jst.go.jp/article/elex/11/10/11_11.20140203/_pdf
• Text Lang: en
• Data Source:
  • JaLC
  • Crossref
  • CiNii Articles
  • KAKEN
• Abstract License Flag: Disallowed