Large-Scale Integrated Circuit Design Based on a Nb Nine-Layer Structure for Reconfigurable Data-Path Processors

• FUJIMAKI Akira

  Nagoya University

• TANAKA Masamitsu

  Nagoya University

• KASAGI Ryo

  Nagoya University

• TAKAGI Katsumi

  Nagoya University

• OKADA Masakazu

  Nagoya University

• HAYAKAWA Yuhi

  Nagoya University

• TAKATA Kensuke

  Nagoya University

• AKAIKE Hiroyuki

  Nagoya University

• YOSHIKAWA Nobuyuki

  Yokohama National University

• NAGASAWA Shuichi

  AIST

• TAKAGI Kazuyoshi

  Kyoto University

• TAKAGI Naofumi

  Kyoto University

Abstract

We describe a large-scale integrated circuit (LSI) design of rapid single-flux-quantum (RSFQ) circuits and demonstrate several reconfigurable data-path (RDP) processor prototypes based on the ISTEC Advanced Process (ADP2). The ADP2 LSIs are made up of nine Nb layers and Nb/AlO_x/Nb Josephson junctions with a critical current density of 10kA/cm², allowing higher operating frequencies and integration. To realize truly large-scale RSFQ circuits, careful design is necessary, with several compromises in the device structure, logic gates, and interconnects, balancing the competing demands of integration density, design flexibility, and fabrication yield. We summarize numerical and experimental results related to the development of a cell-based design in the ADP2, which features a unit cell size reduced to 30-µm square and up to four strip line tracks in the unit cell underneath the logic gates. The ADP LSIs can achieve ∼10 times the device density and double the operating frequency with the same power consumption per junction as conventional LSIs fabricated using the Nb four-layer process. We report the design and test results of RDP processor prototypes using the ADP2 cell library. The RDP processors are composed of many arrays of floating-point units (FPUs) and switch networks, and serve as accelerators in a high-performance computing system. The prototypes are composed of two-dimensional arrays of several arithmetic logic units instead of FPUs. The experimental results include a successful demonstration of full operation and reconfiguration in a 2×2 RDP prototype made up of 11.5k junctions at 45GHz after precise timing design. Partial operation of a 4×4 RDP prototype made up of 28.5k-junctions is also demonstrated, indicating the scalability of our timing design.

Journal

• IEICE Transactions on Electronics

  IEICE Transactions on Electronics E97.C (3), 157-165, 2014

  The Institute of Electronics, Information and Communication Engineers

Keywords

• advanced process
• cell-based design technique
• high-end computing
• large-scale integration
• rapid single-flux-quantum circuits

Details

• CRID: 1390282679354287104
• NII Article ID: 130003394702
• DOI: 10.1587/transele.e97.c.157
• ISSN: 17451353
• ISSN: 09168524
• Web Site: https://www.jstage.jst.go.jp/article/transele/E97.C/3/E97.C_157/_pdf
• Text Lang: en
• Data Source:
  • JaLC
  • Crossref
  • CiNii Articles
  • KAKEN
• Abstract License Flag: Disallowed