Design and High-Speed Demonstration of Single-Flux-Quantum Bit-Serial Floating-Point Multipliers Using a 10kA/cm<sup>2</sup> Nb Process

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Author(s)

    • PENG Xizhu
    • Department of Electrical and Computer Engineering, Yokohama National University
    • YAMANASHI Yuki
    • Department of Electrical and Computer Engineering, Yokohama National University
    • YOSHIKAWA Nobuyuki
    • Department of Electrical and Computer Engineering, Yokohama National University
    • TAKAGI Naofumi
    • Department of Communications and Computer Engineering, Kyoto University
    • TAKAGI Kazuyoshi
    • Department of Communications and Computer Engineering, Kyoto University
    • HIDAKA Mutsuo
    • National Institute of Advanced Industrial Science and Technology (AIST)

Abstract

Recently, we proposed a new data-path architecture, named a large-scale reconfigurable data-path (LSRDP), based on single-flux-quantum (SFQ) circuits, to establish a fundamental technology for future high-end computers. In this architecture, a large number of SFQ floating-point units (FPUs) are used as core components, and their high performance and low power consumption are essential. In this research, we implemented an SFQ half-precision bit-serial floating-point multiplier (FPM) with a target clock frequency of 50GHz, using the AIST 10kA/cm<sup>2</sup> Nb process. The FPM was designed, based on a systolic-array architecture. It contains 11,066 Josephson junctions, including on-chip high-speed test circuits. The size and power consumption of the FPM are 6.66mm × 1.92mm and 2.83mW, respectively. Its correct operation was confirmed at a maximum frequency of 93.4GHz for the exponent part and of 72.0GHz for the significand part by on-chip high-speed tests.

Journal

  • IEICE Transactions on Electronics

    IEICE Transactions on Electronics E97.C(3), 188-193, 2014

    The Institute of Electronics, Information and Communication Engineers

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