A Body Bias Generator with Low Supply Voltage for Within-Die Variability Compensation

• KAMAE Norihiro

  Department of Communications and Computer Engineering, Graduate School of Informatics, Kyoto University

• TSUCHIYA Akira

  Department of Communications and Computer Engineering, Graduate School of Informatics, Kyoto University

• ONODERA Hidetoshi

  Department of Communications and Computer Engineering, Graduate School of Informatics, Kyoto University CREST, JST

Abstract

A body bias generator (BBG) for fine-grained body biasing (FGBB) is proposed. The FGBB is effective to reduce variability and power consumption in a system-on-chip (SoC). Since FGBB needs a number of BBGs, the BBG is preferred to be implemented in cell-based design procedure. In the cell-based design, it is inefficient to provide an extra supply voltage for BBGs. We invented a BBG with switched capacitor configuration and it enables BBG to operate with wide range of the supply voltage from 0.6V to 1.2V. We fabricated the BBG in a 65nm CMOS process to control 0.1mm² of core circuit with the area overhead of 1.4% for the BBG.

Journal

• IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences

  IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences E97.A (3), 734-740, 2014

  The Institute of Electronics, Information and Communication Engineers

Keywords

• body bias generator
• dynamic voltage frequency scaling
• analog-assisted digital
• low supply voltage

Details

• CRID: 1390282681286721280
• NII Article ID: 40019997257
• NII Article ID: 130003394776
• NII Book ID: AA10826239
• DOI: 10.1587/transfun.e97.a.734
• ISSN: 17451337
• ISSN: 09168508
• NDL BIB ID: 025304427
• Web Site: https://ndlsearch.ndl.go.jp/books/R000000004-I025304427
• Web Site: https://www.jstage.jst.go.jp/article/transfun/E97.A/3/E97.A_734/_pdf
• Text Lang: en
• Data Source:
  • JaLC
  • NDL
  • Crossref
  • CiNii Articles
  • KAKEN
• Abstract License Flag: Disallowed