Effect of Cracks on Stress Reduction in GaAs/Si Heterostructures.

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  • Nakajima Kazuo
    ULSI Crystals Laboratory, Fujitsu Laboratories Ltd., 10–1, Morinosato–Wakamiya, Atsugi 243–01, Japan
  • Ochiai Shojiro
    Mesoscopic Materials Research Center, Faculty of Engineering, Kyoto University, Sakyo–ku, Kyoto 606, Japan

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The longitudinal stress distribution in GaAs/Si heterostructure was calculated using improved shear lag analysis. In this analysis, it is assumed that each layer consists of many imaginary thin layers in order to calculate internal stress distributions over the entire the heterostructure. This method is applied to stress calculation in a GaAs/Si heterostructure whose GaAs layer has cracks, in order to determine the effect of cracks on the reduction of stress in the wafer. In the stress distribution in the Si layer close to the heterointerface, a sharp and deep valley of compressive stress appears near cracks. The stress between cracks is maximum in the Si and GaAs layers. The stress in the GaAs layer can be clearly reduced by introducing cracks regardless of wafer length, and it can be greatly reduced by shortening the distance between cracks. The reduction becomes marked for distance less than 100 µ m.

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