Pt/BaxSr(1-x)TiO3/Pt Capacitor Technology for 0.15 .MU.m Embedded Dynamic Random Access Memory

• Tsunemine Yoshikazu

  LSI Manufacturing Technology Unit, Wafer Process Engineering Development Division, Renesas Technology Corp.

• Okudaira Tomonori

  LSI Manufacturing Technology Unit, Wafer Process Engineering Development Division, Renesas Technology Corp.

• Kashihara Keiichiro

  LSI Manufacturing Technology Unit, Wafer Process Engineering Development Division, Renesas Technology Corp.

• Yutani Akie

  LSI Manufacturing Technology Unit, Wafer Process Engineering Development Division, Renesas Technology Corp.

• Shinkawata Hiroki

  LSI Manufacturing Technology Unit, Wafer Process Engineering Development Division, Renesas Technology Corp.

• Mazumder Motaharul Kabir

  LSI Manufacturing Technology Unit, Wafer Process Engineering Development Division, Renesas Technology Corp.

• Ohno Yoshikazu

  LSI Manufacturing Technology Unit, Wafer Process Engineering Development Division, Renesas Technology Corp.

• Yoneda Masahiro

  LSI Manufacturing Technology Unit, Wafer Process Engineering Development Division, Renesas Technology Corp.

• Okuno Yasutoshi

  ULSI Process Technology Development Center, Semiconductor Company, Matsushita Electronics Corp.

• Tsuzumitani Akihiko

  ULSI Process Technology Development Center, Semiconductor Company, Matsushita Electronics Corp.

• Ogawa Hisashi

  ULSI Process Technology Development Center, Semiconductor Company, Matsushita Electronics Corp.

• Mori Yoshihiro

  ULSI Process Technology Development Center, Semiconductor Company, Matsushita Electronics Corp.

Bibliographic Information

Other Title

• Pt/Ba_xSr_(1-x)TiO₃/Pt Capacitor Technology for 0.15 µm Embedded Dynamic Random Access Memory

Abstract

A novel capacitor technology has been developed for 0.15 μm embedded dynamic random access memory (DRAM). Platinum as electrodes and barium strontium titanate (BST) as dielectrics are used in the capacitor. The BST dielectrics is a stack of two layers. The nucleating bottom layer is deposited by sputtering and the top bulk layer is deposited by chemical vapor deposition (CVD). The two-step deposition process is established with high reliability without N₂ high-temperature annealing. Moreover, both thermal stability and reductive stability of the BST capacitors are improved by introducing modulated oxygen-doping into the Pt top electrodes. The degradation mechanism of the BST capacitors by annealing in the back end process was revealed. Oxygen atoms doped into the top electrode diffuse to the interface between the bottom electrode and the metal nitride barrier layer, and oxidize the metal nitride. The modified BST capacitors maintained low leakage current and sufficient capacitance after 500°C N₂ annealing and 400°C H₂ annealing. These BST capacitors have been integrated into the 0.15 μm rule-embedded DRAM having a capacitor under bit-line (CUB) structure and four-level metallizations.

Journal

• Japanese Journal of Applied Physics

  Japanese Journal of Applied Physics 43 (5A), 2457-2461, 2004

  The Japan Society of Applied Physics

Keywords

• BST
• perovskite oxides
• platinum
• MIM
• capacitors
• dielectrics
• leakage current

Details

• CRID: 1390282681243297408
• NII Article ID: 210000055458
• NII Article ID: 130004531988
• DOI: 10.1143/jjap.43.2457
• ISSN: 13474065
• ISSN: 00214922
• Web Site: https://iopscience.iop.org/article/10.1143/JJAP.43.2457
• Web Site: https://iopscience.iop.org/article/10.1143/JJAP.43.2457/pdf
• Text Lang: en
• Data Source:
  • JaLC
  • Crossref
  • CiNii Articles
• Abstract License Flag: Disallowed