A Delay-variation-aware High-level Synthesis Algorithm for RDR Architectures
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As device feature size drops, interconnection delays often exceed gate delays. We have to incorporate interconnection delays even in high-level synthesis. Using RDR architectures is one of the effective solutions to this problem. At the same time, process and delay variation also becomes a serious problem which may result in several timing errors. How to deal with this problem is another key issue in high-level synthesis. In this paper, we propose a delay-variation-aware high-level synthesis algorithm for RDR architectures. We first obtain a <i>non-delayed</i> scheduling/binding result and, based on it, we also obtain a <i>delayed</i> scheduling/binding result. By adding several extra functional units to <i>vacant</i> RDR islands, we can have a delayed scheduling/binding result so that its latency is not much increased compared with the non-delayed one. After that, we <i>similarize</i> the two scheduling/binding results by repeatedly modifying their results. We can finally realize non-delayed and delayed scheduling/binding results simultaneously on RDR architecture with almost no area/performance overheads and we can select either one of them depending on post-silicon delay variation. Experimental results show that our algorithm successfully reduces delayed scheduling/binding latency by up to 42.9% compared with the conventional approach.
- IPSJ Transactions on System LSI Design Methodology
IPSJ Transactions on System LSI Design Methodology 7(0), 81-90, 2014
Information Processing Society of Japan