Residual Voids in Degassing Process of Encapsulation Gel for Power Semiconductor Devices

• Sato Masahiro

  The University of Tokyo

• Kumada Akiko

  The University of Tokyo

• Hidaka Kunihiko

  The University of Tokyo

• Yamashiro Keisuke

  Fuji Electric Co., Ltd.

• Hayase Yuji

  Fuji Electric Co., Ltd.

• Takano Tetsumi

  Fuji Electric Co., Ltd.

Bibliographic Information

Other Title

• パワー半導体デバイス封止用ゲル中におけるボイド残留の一検討

Abstract

Residual voids in degassing process of encapsulation gel for a power device limit the lifetime and the performance of the device itself because of the partial discharges occurrence in it. In this paper the limit of the degassing capability is evaluated based on the equation of equilibrium. It turns out that the gas in defects such as holes and cracks at the rim of the chip-mounted electrode on ceramic substrates cannot be completely removed by vacuum degassing. Then the size of voids that are likely to form in defects is also calculated with a simple model. This analysis is also experimentally checked with a pierced PMMA plate. The measured results can be explained well by the above mentioned model.

Journal

• IEEJ Transactions on Fundamentals and Materials

  IEEJ Transactions on Fundamentals and Materials 134 (6), 432-433, 2014

  The Institute of Electrical Engineers of Japan

Keywords

• power semiconductor devices
• gel
• void

Details

• CRID: 1390282679574736128
• NII Article ID: 130004869392
• DOI: 10.1541/ieejfms.134.432
• ISSN: 13475533
• ISSN: 03854205
• Web Site: https://www.jstage.jst.go.jp/article/ieejfms/134/6/134_432/_pdf
• Text Lang: ja
• Data Source:
  • JaLC
  • Crossref
  • CiNii Articles
  • KAKEN
• Abstract License Flag: Disallowed