Energy-efficient High-level Synthesis for HDR Architecture with Multi-stage Clock Gating

Access this Article

Author(s)

    • Abe Shin-ya
    • Department of Computer Science and Engineering, Waseda University
    • Togawa Nozomu
    • Department of Computer Science and Engineering, Waseda University

Abstract

With the miniaturization and high performance of current and future LSIs, demand for portable devices has much more increased. Especially the problems of battery runtime and device overheating have occurred. In addition, with the downsize of the LSI design process, the ratio of an interconnection delay to a gate delay has continued to increase. High-level synthesis to estimate the interconnection delays and reduce energy consumption is essential. In this paper, we propose a high-level synthesis algorithm based on HDR architectures (huddle-based distributed register architectures) utilizing multi-stage clock gating. By increasing the number of clock gating stages in each huddle, we increase the number of the control steps at which we can apply the clock gating to registers. We can determine the configuration of the clock gating with optimized energy consumption. The experimental results demonstrate that our proposed algorithm reduced energy consumption by up to 27.7% compared with conventional algorithms.

Journal

  • Information and Media Technologies

    Information and Media Technologies 10(1), 1-7, 2015

    Information and Media Technologies Editorial Board

Codes

  • NII Article ID (NAID)
    130004946342
  • Text Lang
    ENG
  • Data Source
    J-STAGE 
Page Top