A Co-Processor Design for an Energy Efficient Reconfigurable Accelerator CMA

• Izawa Mai

  Keio University

• Ozaki Nobuaki

  Keio University

• Koizumi Yusuke

  Keio University

• Uno Rie

  Keio University

• Amano Hideharu

  Keio University

Abstract

Cool Mega Array (CMA) is an energy efficient reconfigurable accelerator consisting of a large PE array with combinatorial circuits and a small microcontroller. In order to enhance the energy efficiency of the total system, a co-processor design of CMA called CMA-Geyser is proposed. By partly replacing the programmable microcontroller by the host processor Geyser with a dedicated hardware controller, the setting up for the CMA and data transfer can be efficiently done.The design using 65nm CMOS process is compared with an off-loading style multicore system Cube-1. By eliminating the data memory required in Cube-1, CMA-Geyser reduced 21.3% of semiconductor area. Also, it achieved about 2.7 times performance of Cube-1 by the efficient data communication between host and the accelerator.

Journal

• International Journal of Networking and Computing

  International Journal of Networking and Computing 5 (1), 239-251, 2015

  IJNC Editorial Committee

Details

• CRID: 1390282680727586304
• NII Article ID: 130005058795
• DOI: 10.15803/ijnc.5.1_239
• ISSN: 21852847
• ISSN: 21852839
• NDL BIB ID: 026076050
• Web Site: https://ndlsearch.ndl.go.jp/books/R000000004-I026076050
• Text Lang: en
• Data Source:
  • JaLC
  • NDL
  • Crossref
  • CiNii Articles
• Abstract License Flag: Disallowed