Through Chip Interface Based Three-Dimensional FPGA Architecture Exploration

• HSU Li-Chung

  Keio University

• MOTOMURA Masato

  Hokkaido University

• TAKE Yasuhiro

  Keio University

• KURODA Tadahiro

  Keio University

抄録

This paper presents work on integrating wireless 3-D interconnection interface, namely ThruChip Interface (TCI), in three-dimensional field-programmable gate array (3-D FPGA) exploration tool (TPR). TCI is an emerging 3-D IC integration solution because of its advantages over cost, flexibility, reliability, comparable performance, and energy dissipation in comparison to through-silicon-via (TSV). Since the communication bandwidth of TCI is much higher than FPGA internal logic signals, in order to fully utilize its bandwidth, the time-division multiplexing (TDM) scheme is adopted. The experimental results show 25% on average and 58% at maximum path delay reduction over 2-D FPGA when five layers are used in TCI based 3-D FPGA architecture. Although the performance of TCI based 3-D FPGA architecture is 8% below that of TSV based 3-D FPGA on average, TCI based architecture can reduce active area consumed by vertical communication channels by 42% on average in comparison to TSV based architecture and hence leads to better delay and area product.

収録刊行物

• IEICE Transactions on Electronics

  IEICE Transactions on Electronics E98.C (4), 288-297, 2015

  一般社団法人 電子情報通信学会

キーワード

• TCI
• ThruChip
• 3-D FPGA
• TSV
• FPGA
• TPR
• VPR

詳細情報

• CRID: 1390282679353967232
• NII論文ID: 130005061833
• DOI: 10.1587/transele.e98.c.288
• ISSN: 17451353
• ISSN: 09168524
• Web Site: https://www.jstage.jst.go.jp/article/transele/E98.C/4/E98.C_288/_pdf
• 本文言語コード: en
• データソース種別:
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