An Energy-Efficient Floorplan Driven High-Level Synthesis Algorithm for Multiple Clock Domains Design

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Author(s)

    • ABE Shin-ya
    • Department of Computer Science and Engineering, Waseda University
    • SHI Youhua
    • Waseda Institute for Advanced Study, Waseda University
    • USAMI Kimiyoshi
    • Department of Computer Science and Engineering, Waseda University|Department of Information Science and Engineering, Shibaura Institute of Technology|Department of Electronic and Photonic Systems, Waseda University
    • TOGAWA Nozomu
    • Department of Computer Science and Engineering, Waseda University

Abstract

In this paper, we first propose an HDR-mcd architecture, which integrates periodically all-in-phase based multiple clock domains and multi-cycle interconnect communication into high-level synthesis. In HDR-mcd, an entire chip is divided into several huddles. Huddles can realize synchronization between different clock domains in which interconnection delay should be considered during high-level synthesis. Next, we propose a high-level synthesis algorithm for HDR-mcd, which can reduce energy consumption by optimizing configuration and placement of huddles. Experimental results show that the proposed method achieves 32.5% energy-saving compared with the existing single clock domain based methods.

Journal

  • IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences

    IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences E98.A(7), 1376-1391, 2015

    The Institute of Electronics, Information and Communication Engineers

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