Statistical Timing Modeling Based on a Lognormal Distribution Model for Near-Threshold Circuit Optimization

• SHIOMI Jun

  Department of Communications and Computer Engineering, Kyoto University

• ISHIHARA Tohru

  Department of Communications and Computer Engineering, Kyoto University

• ONODERA Hidetoshi

  Department of Communications and Computer Engineering, Kyoto University

Abstract

Near-threshold computing has emerged as one of the most promising solutions for enabling highly energy efficient and high performance computation of microprocessors. This paper proposes architecture-level statistical static timing analysis (SSTA) models for the near-threshold voltage computing where the path delay distribution is approximated as a lognormal distribution. First, we prove several important theorems that help consider architectural design strategies for high performance and energy efficient near-threshold computing. After that, we show the numerical experiments with Monte Carlo simulations using a commercial 28nm process technology model and demonstrate that the properties presented in the theorems hold for the practical near-threshold logic circuits.

Journal

• IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences

  IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences E98.A (7), 1455-1466, 2015

  The Institute of Electronics, Information and Communication Engineers

Keywords

• near-threshold computing
• statistical static timing analysis (SSTA)

Details

• CRID: 1390001206310909568
• NII Article ID: 130005085789
• NII Book ID: AA10826239
• DOI: 10.1587/transfun.e98.a.1455
• ISSN: 17451337
• ISSN: 09168508
• HANDLE: 2433/202109
• Web Site: https://www.jstage.jst.go.jp/article/transfun/E98.A/7/E98.A_1455/_pdf
• Text Lang: en
• Data Source:
  • JaLC
  • IRDB
  • Crossref
  • CiNii Articles
  • KAKEN
• Abstract License Flag: Disallowed