Layout Generator with Flexible Grid Assignment for Area Efficient Standard Cell
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- Nishizawa Shinichi
- Graduate School of Science and Engineering, Saitama University
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- Ishihara Tohru
- Graduate School of Informatics, Kyoto University
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- Onodera Hidetoshi
- Graduate School of Informatics, Kyoto University
抄録
This paper discusses a standard cell layout generator that can be used to generate a standard cell library optimized to a target application. It can generate an area efficient layout from a virtual-grid symbolic layout with the ability of flexible grid positioning that considers local design rules enforced in a scaled technology. The generator reduces the cost of library design and enables an optimization of each cell with detailed layout information that can be used to estimate the performance of the cell under design. A standard cell library has been generated for commercial 28-nm FDSOI CMOS process using the proposed layout generator, and used for circuit design. Correct operation of designed circuit is observed form fabricated chip test.
収録刊行物
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- IPSJ Transactions on System LSI Design Methodology
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IPSJ Transactions on System LSI Design Methodology 8 (0), 131-135, 2015
一般社団法人 情報処理学会
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詳細情報 詳細情報について
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- CRID
- 1390282680268711936
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- NII論文ID
- 130005091214
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- ISSN
- 18826687
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- 本文言語コード
- en
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- データソース種別
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- JaLC
- Crossref
- CiNii Articles
- KAKEN
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- 抄録ライセンスフラグ
- 使用不可