Layout Generator with Flexible Grid Assignment for Area Efficient Standard Cell

• Nishizawa Shinichi

  Graduate School of Science and Engineering, Saitama University

• Ishihara Tohru

  Graduate School of Informatics, Kyoto University

• Onodera Hidetoshi

  Graduate School of Informatics, Kyoto University

Abstract

This paper discusses a standard cell layout generator that can be used to generate a standard cell library optimized to a target application. It can generate an area efficient layout from a virtual-grid symbolic layout with the ability of flexible grid positioning that considers local design rules enforced in a scaled technology. The generator reduces the cost of library design and enables an optimization of each cell with detailed layout information that can be used to estimate the performance of the cell under design. A standard cell library has been generated for commercial 28-nm FDSOI CMOS process using the proposed layout generator, and used for circuit design. Correct operation of designed circuit is observed form fabricated chip test.

Journal

• IPSJ Transactions on System LSI Design Methodology

  IPSJ Transactions on System LSI Design Methodology 8 (0), 131-135, 2015

  Information Processing Society of Japan

Keywords

• standard cell library
• Computer-Aided Design
• layout generator

Details

• CRID: 1390282680268711936
• NII Article ID: 130005091214
• DOI: 10.2197/ipsjtsldm.8.131
• ISSN: 18826687
• Web Site: https://www.jstage.jst.go.jp/article/ipsjtsldm/8/0/8_131/_pdf
• Text Lang: en
• Data Source:
  • JaLC
  • Crossref
  • CiNii Articles
  • KAKEN
• Abstract License Flag: Disallowed