A Novel Load Regulation Technique for Power-SoC with Parallel-Connected POLs
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- Abe Seiya
- Kyushu Institute of Technology
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- Matsumoto Satoshi
- Kyushu Institute of Technology
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- Ninomiya Tamotsu
- City of Kitakyushu, New Industry Promotion Division
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抄録
This paper presents a novel load regulation technique for parallel-connected POLs which reads for power supply on chip (power-SoC). In power-SoCs, many POLs are implemented on the same chip. In this case, the conventional loop control (feedback control) may have problems such as oscillation. The proposed strategy regulates the output voltage by changing the number of working POLs under fixed duty ratio. The parallely connected POL system is implemented using MATLAB/Simulink, and the operating characteristics are confirmed. In addition, the proposed control strategy is also verified experimentally.
収録刊行物
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- IEEJ Journal of Industry Applications
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IEEJ Journal of Industry Applications 4 (6), 732-737, 2015
一般社団法人 電気学会
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詳細情報
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- CRID
- 1390282680393213696
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- NII論文ID
- 130005107045
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- ISSN
- 21871108
- 21871094
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- NDL書誌ID
- 026859640
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- 本文言語コード
- en
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- データソース種別
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- JaLC
- NDL
- Crossref
- CiNii Articles
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- 抄録ライセンスフラグ
- 使用不可