Low-Power Single-Slope Analog-to-Digital Converter with Intermittently Working Time-to-Digital Converter

この論文にアクセスする

著者

    • Uchida Daisuke
    • Graduate School of Information Science and Technology, Hokkaido University
    • Ikebe Masayuki
    • Graduate School of Information Science and Technology, Hokkaido University
    • Motohisa Junichi
    • Graduate School of Information Science and Technology, Hokkaido University
    • Sano Eiichi
    • Research Center for Integrated Quantum Electronics, Hokkaido University

抄録

We propose a single-slope analog-to-digital converter (ADC) with an intermittently working time-to-digital converter (TDC). Applying an n-bit TDC reduces the conversion time by a factor of 2<sup>n</sup>, and using multiphase clock signals achieves timing consistency and realizes robust metastability. We focus on the operation time of the TDC. Since a TDC must operate continuously, it requires a large dissipation power. We propose generating the pulse-width modulation (PWM) signal of a single-slope ADC and apply a scheme for limiting the TDC operation period in order to reduce the TDC power dissipation. We designed and fabricated a 12-bit ADC, which consists of a 6-bit TDC and a 6-bit single-slope ADC, by using a 0.18 μm CMOS process. The ADC operated at 100 kS/s consumed 5.5 μW from a 1 V supply. Its INL and DNL were +1.9/-1.9 LSB and +0.5/-0.8 LSB, respectively.

収録刊行物

  • 信号処理

    信号処理 19(6), 219-226, 2015

    信号処理学会

各種コード

  • NII論文ID(NAID)
    130005110400
  • 本文言語コード
    ENG
  • ISSN
    1342-6230
  • データ提供元
    J-STAGE 
ページトップへ