Data-Transfer-Aware Design of an FPGA-Based Heterogeneous Multicore Platform with Custom Accelerators

• TAKEI Yasuhiro

  Tohoku University

• WAIDYASOORIYA Hasitha Muthumala

  Tohoku University

• HARIYAMA Masanori

  Tohoku University

• KAMEYAMA Michitaka

  Tohoku University

Abstract

For an FPGA-based heterogeneous multicore platform, we present the design methodology to reduce the total processing time considering data-transfer. The reconfigurability of recent FPGAs with hard CPU cores allows us to realize a single-chip heterogeneous processor optimized for a given application. The major problem in designing such heterogeneous processors is data-transfer between CPU cores and accelerator cores. The total processing time with data-transfers is modeled considering the overlap of computation time and data-transfer time, and optimal design parameters are searched for.

Journal

• IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences

  IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences E98.A (12), 2658-2669, 2015

  The Institute of Electronics, Information and Communication Engineers

Keywords

• heterogeneous multicore
• FPGA
• custom accelerators
• reconfigurable architecture

Details

• CRID: 1390282681288989952
• NII Article ID: 130005111969
• DOI: 10.1587/transfun.e98.a.2658
• ISSN: 17451337
• ISSN: 09168508
• Web Site: https://www.jstage.jst.go.jp/article/transfun/E98.A/12/E98.A_2658/_pdf
• Text Lang: en
• Data Source:
  • JaLC
  • Crossref
  • CiNii Articles
  • KAKEN
• Abstract License Flag: Disallowed