A column-parallel clock skew self-calibration circuit for time-resolved CMOS image sensors

• Miao Lianghua

  Research Institute of Electronics, Shizuoka University

• Yasutomi Keita

  Research Institute of Electronics, Shizuoka University

• Imanishi Shoma

  Graduate School of Integrated Science and Technology

• Kawahito Shoji

  Research Institute of Electronics, Shizuoka University

抄録

This letter reports a column-parallel clock skew self-calibration circuit for time-resolved (TR) CMOS image sensors. In TR CMOS imagers, as the time resolution increases, the skew of gating clock between pixels becomes a difficult problem because the clock skew causes the reduction of measurable maximum range in particular pixels or unmeasurable pixels. To calibrate the skew in short time, a column-parallel skew self-calibration circuit based on two-stage delay line and a dual clock tree is proposed. The experimental results show that the skew calibration circuit successfully reduces the skew from 247 ps_rms to 25 ps_rms, and the calibration time is only 12 µs, which is much faster than the previous work.

収録刊行物

• IEICE Electronics Express

  IEICE Electronics Express 12 (24), 20150911-20150911, 2015

  一般社団法人 電子情報通信学会

キーワード

• TR CMOS imager
• column-parallel clock-skew calibration
• dual clock tree

詳細情報

• CRID: 1390001205213268864
• NII論文ID: 130005117176
• DOI: 10.1587/elex.12.20150911
• ISSN: 13492543
• Web Site: https://www.jstage.jst.go.jp/article/elex/12/24/12_12.20150911/_pdf
• 本文言語コード: en
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