Measuring Method for TSV-based Interconnect Resistance in 3D-SIC by Embedded Analog Boundary-Scan Circuit

• Kameyama Shuichi

  Fujitsu Limited

• Baba Masayuki

  Fujitsu Limited

• Higami Yoshinobu

  Graduate School of Science and Engineering, Ehime University

• Takahashi Hiroshi

  Graduate School of Science and Engineering, Ehime University

Abstract

In this paper, we introduce a method to measure the resistance of high density post-bond Through Silicon Via (TSV) including serial micro-bumps and bond resistance in Three Dimensional Stacked IC (3D-SIC). The key idea of our technology is to use Electrical Probes embedded in stacked silicon dies. It is a measuring circuit based on Analog Boundary-Scan (IEEE 1149.4). The standard Analog Boundary-Scan structure is modified to realize high measuring accuracy for TSVs in 3D-SIC. The main contribution of the method is to measure the resistance of high pin count (e.g. >10,000) post-bond TSVs accurately. Electrical Probes correspond to the high density of TSV (e.g. < 40 um pitch) and work like Kelvin probe. The measurement accuracy is less than 10 mΩ. We also introduce the preliminary results of small scale measuring experiments and the results of SPICE simulation of large scale measuring circuits.

Journal

• Transactions of The Japan Institute of Electronics Packaging

  Transactions of The Japan Institute of Electronics Packaging 7 (1), 140-146, 2014

  The Japan Institute of Electronics Packaging

Keywords

• 3D-SIC
• TSV
• Interconnect
• Analog Boundary-Scan
• Resistance Measurement

Details

• CRID: 1390001205314283904
• NII Article ID: 130005130537
• DOI: 10.5104/jiepeng.7.140
• ISSN: 18848028
• ISSN: 18833365
• Web Site: https://www.jstage.jst.go.jp/article/jiepeng/7/1/7_140/_pdf
• Text Lang: en
• Data Source:
  • JaLC
  • Crossref
  • CiNii Articles
  • KAKEN
• Abstract License Flag: Disallowed